Engineers Clinic
ExpertEngineering trackCE-VLSIDE-P10

Full VLSI chip-block project

Build Full VLSI chip-block project end to end using Verilog/VHDL, Cadence, Xilinx. Ten guided workspace steps take you from requirements to a deployed, AI-graded deliverable. Submit: CAD/sim files + design report PDF + results + demo media.

Core EngineeringVLSI Design
10 Guided Steps120h Internship TierSubmit: CAD/sim files + design report PDF + results + demo mediaVerified CertificateAI Rubric Graded
Core Tech Stack:Verilog/VHDLCadenceXilinx
Program Overview

Build Full VLSI chip-block project end to end using Verilog/VHDL, Cadence, Xilinx. Ten guided workspace steps take you from requirements to a deployed, AI-graded deliverable. Submit: CAD/sim files + design report PDF + results + demo media.

What you submit

CAD/sim files + design report PDF + results + demo media

Stack: Verilog/VHDL, Cadence, Xilinx

How it is graded

Signals: Design correctness; simulation results; standards; report; drawings/BOM

  • Functionality & requirements30
  • Technical quality & architecture25
  • Documentation15
  • Deployment & evidence15
  • Innovation10
  • Presentation5

Pass 60% · Merit 75% · Distinction 90%

Learning Outcomes
Graded on: Design correctness; simulation results; standards; report; drawings/BOM. Pass 60% · Merit 75% · Distinction 90%.
Target Audience

Engineering Students

Diploma, B.Tech, B.E., BCA, MCA, or M.Tech students seeking practical experience.

Aspiring Developers

Developers who want to build proof-of-work capstone projects for tech resumes.

Job Seekers

Graduates looking for AI-evaluated code review & verified industry credentials.